Modern Analog to Digital Converters (ADCs) are timed based on a user supplied low jitter external clock source. These ADCs often operate on both phases of this clock signal to increase both efficiency and throughput. ADCs are specified to operate with a clock signal having a duty cycle that varies across a certain range. As is well known, a clock signal's duty cycle refers to a ratio of one clock phase width to the entire clock period. An ADC capable of operating over a wider duty cycle range can be beneficial in that the ADC is more flexible and useful across a larger set of applications.
A problem exists with prior art ADCs having the capability of operating over a wider clock signal duty cycle. Such prior art ADCs have internal circuitry configured to function with wide-ranging duty cycles. This circuitry unfortunately also increases the power needed to achieve high performance. Excessive power requirements leads to a number of disadvantages. For example, in handheld applications, an excessive power requirement reduces the battery life of a device. In other applications, excessive power requirements can lead to heat dissipation problems, noise problems, and other types of unreliability effects.
Thus, what is required is a solution for implementing duty cycle stabilization for an ADC integrated circuit device. The required solution should be capable of producing a clock signal having a duty cycle that is independent of any external clock duty cycle. Additionally, the required solution should be capable of producing a clock signal having a near optimal duty cycle of 50% for lowest power consumption in most ADCs. The present invention provides a novel solution to these requirements.